发明名称 |
Program execution control device having addressability in accordance with M series pseudo-random number sequence |
摘要 |
Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.
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申请公布号 |
US5651123(A) |
申请公布日期 |
1997.07.22 |
申请号 |
US19950460947 |
申请日期 |
1995.06.05 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
NAKAGAWA, SHINICHI;ISHIHARA, KAZUYA;KUMAKI, SATOSHI;HANAMI, ATSUO;SEGAWA, HIROSHI;MATSUMURA, TETSUYA |
分类号 |
G06F9/32;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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