| 摘要 |
A variable length decoder with adaptive acceleration in processing of an encoded input bit stream which includes an input circuit for receiving the input bit stream and for providing a decoding window that includes a sequence of bits which include one or more code words to be decoded at an output thereof, a code word length decoding circuit for determining the combined length of a combination of two or more code words received from the input circuit in response to a first value of a control signal and for generating a combined length signal representative of the determined combined length, and for determining the length of an individual code word received from the input circuit in response to a second value of the control signal and for generating an individual word length signal representative of the determined length of the individual code word, a computation loop circuit for receiving the combined length signal or the individual word length signal from the code word length decoding circuit and, in response thereto, shifting the decoding window to provide a new sequence of bits that include one or more additional code words to be decoded at the output of the input circuit, a code word value decoding circuit for decoding the values of the combination of two or more code words provided by the input circuit in response to the first value of the control signal, and for decoding the value of the individual code word in response to the second value of the control signal, and, a control circuit for generating the control signal, and controlling the operation of the variable length decoder according to a decoding protocol. In the disclosed embodiment, the two or more code words of the combination of code words are part of a selected group of code words in a Huffman encoded input bit stream whose bit lengths are less than a prescribed number of bits.
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