| 摘要 |
<p>A small-sized inexpensive test pattern generator for a high-speed semiconductor memory having a multi-bit data width. The test pattern generator is provided with a data computing section (30) having a data width which is 1/n of that of a device (5) to be measured, an n-bit register A (141) whose data is set from an instruction memory (131), and (n) control logic sections (151) which control the passing of signals in accordance with the output signal of the register A (141). Alternatively, it is possible to use an AND gate which passes the output signal of the data computing section (30) in accordance with the output signal of the register A (141) and an OR gate which generates a fixed output in place of the control logic sections (151). Further, alternatively, an exclusive OR gate (35) which makes inverting operations in accordance with a flag register (34) can be used.</p> |
