| 摘要 |
PROBLEM TO BE SOLVED: To reduce a hardware scale by permitting arithmetic processing speed to be high, improving a response characteristics and to miniaturize an adder. SOLUTION: A three-fold sampling part 5 executes a three-fold time division processing to the high-speed one bit signals S1 , S2 and S3 at every signal, which are obtained byΣΔ-modulating a three-channel input analog signal by a sampling frequency fS so as to output a three-channel time division signal S4 . A first stage integrater 8 integrates the three-channel time division signal S4 from a three-fold sampling equipment 5 by a 3fS cycle through the use of a one- sample delay equipment 7 and the adder 6. A one-bit quantizing equipment 9 re-quantizes an integration output from the first stage integrater 8 into anΣΔ-modulating signal by fS. A gain adjusting equipment 11 permits the delay output from the one-sample delay equipment 10 to be the one-third of it. Moreover, the output from the gain adjusting equipment 11, the output from the one-sample delay equipment 7 and the three-channel time division signal S4 from the three-fold sampling equipment 5 are added.
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