Signal level converter circuit with two CMOS inverting stages

摘要

The circuit operates on a binary input signal (UE) whose high level is of the order of the lower supply voltage (UL), e.g. 5 V. The first invertor (10) has complementary MOSFETs (M10,M11) and a blocking diode (D). Its output (12) feeds the second invertor (20) whose input (21) is connected to the higher supply voltage (UH) of e.g. 10 V by a switching stage (30). This comprises two p-channel MOSFETs (M30,M31) connected in series and driven by the output and input voltages (UA,UE) respectively.