| 摘要 |
A variable length coder is disclosed having a ping-pong zig-zag RAM, a zig-zag FIFO and a variable length integer (VLI), variable length code word (VLC) mixer. The ping-pong zig-zag RAM has a first RAM for processing each odd ordinalled block of the inputted sequence of blocks and a second RAM for processing each even numbered block of the inputted sequence of blocks. The zig-zag FIFO has a comparator circuit, a counter and a FIFO. The comparator circuit is for determining whether or not an inputted coefficient is equal to zero. If the coefficient is non-zero, it is stored in the FIFO. If the coefficient equals zero, the counter increments a count maintained therein. The counter counts the number of zeros in each continuous sequence of zero coefficients in each block and outputs the count for each sequence of zeros for storage in the FIFO. The VLI,VLC mixer has a decoder for receiving the length of a VLC for each VLI,VLC pair and for outputting a mask word depending on the inputted VLC length. The VLI,VLC mixer also has a barrel shifter for receiving the VLI,VLC and VLC length. Using the mask word, the barrel shifter shifts the VLI to particular bit positions of a shifter register therein and inserts the VLC immediately adjacent to the shifted VLI.
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