| 摘要 |
The variable length decoding circuit is comprised of a first table consisting of PLA structure stores a header information only and, upon 16-bit data being applied from a multiplexer(22), outputs the corresponding code and code length of the header information; the output header information is transmitted to a second table(25), the code length is transmitted to a rotator(24) and a latch(26); the rotator(24) outputs a word of a transformation code consisting of a run and level corresponding to the header information in unit of half clock; the latch(26) is synchronized to a rising edge of a clock signal to latch a code length data, the latched data is transmitted to a barrel shifter(21) and an adder(27); the adder(27) adds the code length upon falling of the clock signal provided from the latch(26) and the code length upon rising of the clock signal provided from the first table(23), then outputs the result to a data transmission processing part(11). |
