| 摘要 |
If FIFO writing control signal generating part(35) detects frame starting flag by flag detecting part, it outputs clock synchronous signal and makes writing call signal enable, and if ending flag or pause state is detected by flag detecting part(32) and pause state part(33), it makes writing call signal disable. FIFO writing control part(36) receives writing call signal of FIFO writing control signal generating part(35) and clock signal having same frequency as receiving synchronous clock, and distributes those so that outputs data writing control signal and multiplexing control signal. FIFO(39) stores and outputs data outputting from multiplexor(38) by control of data writing control signal in regular order.
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