| 摘要 |
FIFO buffer system capable of effectively controlling write and read operations thereof comprises N number of cascaded FIFO buffers, each of the cascaded FIFO buffers sequentially storing the input digital data in response to a write signal, sequentially generating the output digital data in response to a read signal and generating storage state signals including a full flag and an empty flag signals representative of the full and empty states thereof, respectively, N being a positive integer larger than 3; a clock for generating a second clock signal; first control means, in response to the full flag signals from the cascaded FIFO buffers, for generating the write signal synchronized with the first clock signal if fewer than (N-1) cascaded FIFO buffers are full; and second control means, in response to the empty flag signals from the cascaded FIFO buffers, for initiating a read operation by generating the read signal synchronized with the second clock if first three cascaded FIFO buffers, which have sequentially stored the input digital data, are not in the empty state, and for terminating the read operation, in response to the write signal and the END signal, after the last bit of the input data is read from the cascaded FIFO buffers.
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