| 摘要 |
There is provided a phase adjusting circuit of a particular signal in a radio base station in which a master system is connected through a iom2 bus with a slave system, comprising: a frequency generating means which generates a high frequency clock signal higher than a frequency of data clock output through the iom2 bus; a frame reset signal generating means which generates a reset signal having a pulse width shorter than that of a frame synchronous signal; a data clock setting means which generates a predetermined position detecting signal of the data clock; a data clock reset generating means which generates a clear signal having a pulse width shorter than that of the data clock signal; a gate signal generating means which generates a gate signal with respect to one data of DDN during 2 cycles of the data clock signal; a phase adjusting means which adjusts a phase of the preset data clock and outputs the adjusted data.
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