| 摘要 |
PROBLEM TO BE SOLVED: To form a phase locked loop (PLL) in a digital circuit. SOLUTION: A synchronizing signal extracted from a video signal is gated by an AND gate 3 through a separator circuit 1, and the gated synchronizing signal is supplied to a phase comparator circuit 4. This compared output is inputted through a loop filter 5 to an oscillation circuit 6 composed of a counter and this oscillated output is inputted to the phase comparator circuit 4, so that the PLL can be formed. Further a mask signal generating circuit 10 generates that mask signal from the output of this oscillation circuit 6 and a counter 13 counts how many times the synchronizing signals are continuously absent during the period of this mask signal. When this number of times exceeds a prescribed value, the synchronizing signal from the video signal is extracted and corresponding to this signal, the counter consisting of the oscillation circuit is reset. Thus, the stable and speedy PLL and synchronizing separator circuit are constituted. |
