Fast fourier transform dedicated processor

摘要

A Fast Fourier Transform (FFT) dedicated processor includes a scrambler SM scrambling a real input data sequence x(i) and thereby providing two scrambled data subsequences a(i) and b(i). A data generation circuit GC coupled to SM provides a complex data sequence y(i) whose real and imaginary parts equal the scrambled data subsequences a(i) and b(i) respectively. y(i) is applied to an arithmetic unit AU, which under the control of a control unit CoM, is successively converted to an arithmetic means AM, a data regeneration circuit RC and a combinatorial means CM. AM generates an intermediate Fast Fourier Transform series Y(i) of y(i). RC splits up Y(i) into Fast Fourier Transform series A(i) and B(i) of a(i) and b(i) respectively and CM executes a final traditional Fast Fourier Transform combinatorial step and produces the Fast Fourier Transform sequence X(i) of the real input data sequence x(i).