| 摘要 |
For a semiconductor memory device comprising, besides a redundant array, memory cells of an ordinary array in links (columns, rows) accessed by an ordinary address signal, an additional address signal of a high level activates, when the ordinary address signal indicates a preliminarily stored faulty link, a redundant circuitry activating signal for suspending operation of an ordinary link selecting circuit to select by a redundant link selecting circuit a substitution link for the faulty link. When given a low level, the additional address signal deactivates the redundant circuitry activating signal to select ordinary links by the ordinary address signal. Before the faulty link is stored, the low level serves as a test mode signal for testing the ordinary and the redundant arrays in a common mode of operation. To be switched by a block switch signal into a bit and a bit-word structure, a memory device may comprise two or more memory blocks, each comprising the ordinary and the redundant arrays, and is preferably supplied additionally with the test mode signal with a high level to test the ordinary and the redundant arrays in individual memory blocks.
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