| 摘要 |
PROBLEM TO BE SOLVED: To directly compare a clock phase with an edge of a signal change in an NRZ signal or an RZ signal. SOLUTION: When an NRZ signal is received from an NRZ signal input terminal 2, a pulse generating circuit 4 provides an output of a pulse with a width of nearly a clock period at an output terminal 14 of the pulse generating circuit 4 corresponding to a leading edge and a trailing edge. Furthermore, a 2nd edge detection circuit 5 and a delay circuit 12 provide an output a short pulse to a 2nd phase comparator input terminal 11 corresponding to the leading edge and the trailing edge. A short pulse is outputted to a 2nd phase comparator input terminal 11. The clock is given to a clock input terminal 1, a short pulse corresponding to the leading by the 1st edge detection circuit 3 is outputted to an output terminal 13 of the 1st edge detection circuit 3, the specific short pulse is selected by an AND gate 6 and outputted to the 1st phase comparator input terminal 10. A phase comparator 7 compares a phase at a 2nd phase comparator input terminal 11 with a phase of a 1st phase comparator input terminal 10 and the result is outputted to a phase advance output terminal 8 and a lag phase output terminal 9. |
