发明名称 |
Memory devices with selectable access type and systems and methods using the same |
摘要 |
<p>A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row. <IMAGE></p> |
申请公布号 |
EP0771007(A2) |
申请公布日期 |
1997.05.02 |
申请号 |
EP19960307293 |
申请日期 |
1996.10.04 |
申请人 |
CIRRUS LOGIC, INC. |
发明人 |
RAO, G.R. MOHAN |
分类号 |
G06F12/02;G11C7/10;G11C11/401;G11C11/41;(IPC1-7):G11C7/00 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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