| 摘要 |
A circuit for generating bit pattern is provided, which includes a first shift register (211) for storing an escape code, a second shift register (209) for storing zero length indicating the number of 0, a third shift register (208) for storing a discrete cosine transform constant which is not 0, a first register (207) for transmitting the discrete cosine transform constant which is not 0 to the third shift register, a counter (202) for counting the number of the discrete cosine transform constant which is 0, a second register (205) for storing a position of a previous variable code, a third register (203) for storing current zero length, an adder (204) for generating new position information for next variable length coding by adding the previous variable length code position with the current zero length, an encoder (206) for producing a signal for selecting a predetermined bit of the second shift register, and a multiplexer (210) for selecting a predetermined bit of the second shift register according to an output from the encoder to output the bit to the first shift register, wherein even in case of an exceptional case, the image compression efficiency according to the variable length code is improved by varying the number of bit for selectively coding zero length in the zig-zag sequence of the variable length code which has been previously coded.
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