发明名称 METHOD FOR GENERATING LSI TEST PATTERN
摘要 PROBLEM TO BE SOLVED: To supply a signal to a LSI internal circuit at the same timing as logic simulation by stopping an optional clock pulse in a plurality of test clocks, and performing the crossing-over of the clock of a signal. SOLUTION: A LSI tester can freely stop and move each clock A, B. The clock A is given from a point P1 to a latch circuit 1 through a buffer 5, and the circuit 1 latches an input signal synchronously with the signal build up at a time T1 in a point P1. The signal is inputted to a latch circuit 2 at the time T1 through the element delay and wiring delay of the circuit 1. The clock pulse CP1 corresponding to the clock B is stopped by the LS1 tester make the circuit 2 latch the signal synchronously with the build up of the following pulse at a time T13. The circuit 2 transmits the signal to an internal circuit L at the timing of a time T14 through element delay and wiring delay. The circuit L transmits the operation result based on the signal to an output pin, and forms the same output expected value as in the case having no delay difference τ.
申请公布号 JPH09105769(A) 申请公布日期 1997.04.22
申请号 JP19950262733 申请日期 1995.10.11
申请人 OKI ELECTRIC IND CO LTD 发明人 AKIYAMA HIROYUKI
分类号 G01R31/3183;G06F11/22;G06F17/50;H01L21/82;H03K19/00 主分类号 G01R31/3183
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