Testverfahren für Elemente von integrierten Schaltungen und dazugehöriges integriertes Element

摘要

The invention relates to on-wafer test of integrated circuits. In order to facilitate the test, a test circuit region (24) is provided on the wafer, including contact heads (28) on which the prods of a tester can be applied, a demultiplexer (30) for transmitting test stimuli to one bus from among N at the output of the demultiplexer. The output buses of the demultiplexer extend between the lines of chips on the wafer. Column selection conductors extend between the columns of chips. The demultiplexer (30) and a column decoder (32), both controlled directly by the tester, make it possible to select one and only one chip (22) in order to test it. The test prods are not moved from one chip to the following one. The wafer is then cut up into individual chips.