发明名称 DATA MULTIPLEXER
摘要 PROBLEM TO BE SOLVED: To output the data of a bit length not to be limited by the number of multiplexing systems with a reduced memory capacity. SOLUTION: When a bit length K equal with a value obtd. by adding an integer A (0<A<N) to the integer (M) multiple of the number N of systems is designated, data stored in a memory 11, are read out successively from a prescribed pair to the M-th pair in the time cycle of N.T with N bits as a pair. An operation of reading the (M+1)th pair of data at timing of dividing the period of (N+A).T into two periods of more than N.T/2 after the Mth pair of data are read out is repeated at cycles of a K.T time. Synchronously with the reading out of this data from a prescribed pair to the M-th pair, a latch signal is outputted to a latch circuit 14 M times and, an operation of outputting the (M+1)th latch signal at timing of dividing the period of (N+A).T after this M-th latch signal is outputted into the period of A.T and the period of N.T is repeated at cycles of a K.T time.
申请公布号 JPH0998143(A) 申请公布日期 1997.04.08
申请号 JP19950277173 申请日期 1995.09.29
申请人 ANRITSU CORP 发明人 HARADA MITSUO
分类号 G06F12/02;G06F5/00;H04J3/04;(IPC1-7):H04J3/04 主分类号 G06F12/02
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