| 摘要 |
The arrangement comprises a summation/integration network (F), whose input is an input of the arrangement, and which is at least of a third order. The network comprises a forward path having at least three in series connected steps, which each comprise an amplifier for multiplication with forward coefficients (d1...dN), an adder (1...N) and an integrator (H1...HN). The network also comprises a backward path having at least three amplifiers for multiplication with backward coefficients (a1...aN), and having an output coupled to an input of a 1-bit quantiser (ADC). An output of the quantiser provides an output (Y) of the arrangement, and an input to a 1-bit D/A converter, whose output is supplied to the summation/integration network. The coefficients are determined by determining a system function of a linear model for the converter, and using the system function to determine a noise and a maximal value of a signal to noise ratio. A stability condition is determined from the poles of the system function, in response to the coefficients, and overload conditions are determined from a determined non-linear model of the converter. A non-linear optimisation is used to optimise the efficiency under evaluation of the overload and stability conditions.
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