发明名称
摘要 PURPOSE:To efficiently execute a logic simulation by advancing the simulation time of a gate in respective charge without taking a synchronization between respective processors. CONSTITUTION:A message receiving processing part 12 receives an event 11 by a message from a processor 10A. A message transmitting processing part 13 transmits the event 11 generated by the output value of a gate GT served by a local processor 10. Then, a simulation execution processing part 17 calcurates the output value to a time when the output of the gate can be defined based on the time of the event, the present time of an applying pin and the present time of the gate on the respective events of an event cue 14. When the time advances, the new event 11 is generated, and a processing to transmit to the processor 10B and so on through the transmitting processing part 13 is executed. The respective processors act based on the received event asynchronously.
申请公布号 JP2590179(B2) 申请公布日期 1997.03.12
申请号 JP19880033400 申请日期 1988.02.16
申请人 FUJITSU LTD 发明人 SHIMOGOORI SHINTARO;KAGE TETSUO
分类号 G06F11/25;G06F11/26;G06F15/16;G06F17/50;G06F19/00 主分类号 G06F11/25
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