| 摘要 |
PROBLEM TO BE SOLVED: To suppress fluctuation in a phase between output clocks of plural PLL circuits connected in cascade when a reference clock is switched. SOLUTION: The circuit is provided with a phase locked loop circuit 3 synchronizing an output clock with an input clock and decreasing a loop gain in response to a request of a hold-over state, a clock selection circuit 1 applying selectively plural reference clocks to the phase locked loop circuit 3, and an input interrupt detection circuit 2 detecting interruption of the selection clock of the clock selection circuit 1, providing an instruction to the clock selection circuit 1 to select other clock, requesting a hold-over state to the phase locked loop circuit 3 and requesting release of the hold-over state after selection of the clock is switched. |
