| 摘要 |
<p>Coefficient data generated in a DCT transform circuit (2Y, 2C) is sent to a shuffling circuit (3Y, 3C). The shuffling circuit shuffles the data in one field. The amount of coefficient data generated block by block is equalized by the shuffling process. A buffering circuit (7) forms sync blocks with a fixed length by using coefficient data. A DC component of coefficient data is followed by low order components, following by high order components. The blocks of coefficient data are sent to the buffering circuit in this sequence. The buffering circuit performs control operations such as moving bits of high order coefficient data to other sync blocks. <IMAGE></p> |
