| 摘要 |
PROBLEM TO BE SOLVED: To decrease the number of external terminal pins of the integrated circuit composed of a PLL and a demodulating circuit which demodulates received data. SOLUTION: A lock detecting circuit 85 which detects the PLL 31 being locked and a frame detecting circuit 84 which detects the frame signal of the received data are provided. A switching circuit 90 is provided which is supplied with the lock detection signal LKD of the lock detecting circuit 85 and the frame detection signal FRMD of the frame detecting circuit 84. The switching circuit 90 is controlled with an external control signal MDPL to selectively lead out the lock detection signal LKD and frame detection signal FRMD. |
