发明名称 Non-delay based address transition detector (ATD)
摘要 A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.
申请公布号 US5606269(A) 申请公布日期 1997.02.25
申请号 US19950548651 申请日期 1995.10.26
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 PONTIUS, DALE E.;TAMLYN, ROBERT
分类号 H03K5/1534;(IPC1-7):H03K19/003 主分类号 H03K5/1534
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