| 摘要 |
<p>PURPOSE:To minimize the risk of the system from entering the pseudo synchronization by varying a reset interval of a scramble pattern and a descramble pattern. CONSTITUTION:A frame insertion circuit 1 constitutes a signal multiplexed by a multiplexer circuit 14 into a frame and outputs the result to a scramble circuit 5. The circuit 5 scrambles a transmission signal of frame configuration with a scramble pattern outputted from a scramble pattern generating circuit 4 and outputs the result to a reception section 17. On the other hand, a demultiplexer circuit 16 of the reception section 17 takes frame synchronization and demultiplexes a signal representing whether or not the scramble pattern is reset from a received data 8 and outputs it to a descramble pattern generating circuit 9. A frame synchronization circuit 7 obtains a synchronization detection signal from the received data 8, outputs it to the circuit 9 and outputs a descramble pattern to a descramble circuit 10, and the output of the demultiplexer circuit 16 is reset once per 3 frames. The circuit 10 descrambles the signal with a correct scramble pattern to output a reception output 11.</p> |
