| 摘要 |
PROBLEM TO BE SOLVED: To detect phase lockout in a PLL circuit accurately without error. SOLUTION: A delay element 11 and an OR circuit 12 generate a signal D1 corresponding to an output signal inverse of Qout from an inverting output terminal inverse of Q of a phase comparator circuit 6 and a signal D2 being an inverted signal of the output signal inverse of Qout . A NOT circuit 15, OR circuits 16, 17 and a delay element 18 generate a signal C1 representing a timing when the signal D1 is logical L at phase locking and a signal C2 representing a timing when the signal D2 is logical L at phase locking. Flip-flop circuits 13, 14 monitor the level of the signals D1, D2 synchronously with the signals C1, C2 and when either of the signals D1, D2 is logical H, it is discriminated as lockout and an OR circuit 19 outputs lockout detection signal Lout at an H level. |
