发明名称 Halterung für flache Schaltungseinheiten und dafür verwendete flache Schaltungseinheiten
摘要 In an electrical wiring system, a typical process for suppressing noise due to electric current consists in preparing a pair of flat circuit units (11, 12, 40, 41) comprising respectively an insulation layer and at least one circuit conductor (13, 14, 15, 16, 42, 43) therein or thereon which undulate to form wave-like patterns and in superposing fixedly said conductor of the first unit (11, 40) with that of the second unit (12, 41) in such that at least one insulation layer is interposed between the superposed conductors and whereby peaks (30) of the second unit conductor (15, 16, 43) face troughs (32) of the first unit conductor (13, 14, 42); according to the invention, fixing is performed by means enabling to interweave said peaks with said troughs. One such means consists in providing the first flat circuit unit with trough-side slits (33) and the second with peak-side slits (31) and in inserting the tongues (34) formed by the trough-side slits in the peak-side slits. Another such means consists in forming a pair of flat circuit units (40, 41) and corresponding circuit conductors (42, 43) into an undulation and in interweaving the pair in alternate upside and downside fashion. <IMAGE> <IMAGE>
申请公布号 DE69401258(D1) 申请公布日期 1997.02.06
申请号 DE1994601258 申请日期 1994.10.18
申请人 SUMITOMO WIRING SYSTEMS, LTD., YOKKAICHI, MIE, JP 发明人 NAKANISHI, RYUJI, C/O SUMITOMO WIRING SYSTEMS LTD., YOKKAICHI-CITY, MIE 510, JP
分类号 H01B7/08;H01B7/00;H01B11/00;H05K1/02;H05K1/11;H05K1/14;H05K9/00;(IPC1-7):H05K9/00 主分类号 H01B7/08
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