发明名称 |
Electrically erasable programmable read-only memory with an array of one-transistor memory cells |
摘要 |
A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.
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申请公布号 |
US5596523(A) |
申请公布日期 |
1997.01.21 |
申请号 |
US19950513000 |
申请日期 |
1995.08.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ENDOH, TETSUO;SHIROTA, RIICHIRO |
分类号 |
G11C17/00;G11C16/02;G11C16/04;G11C16/16;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C7/00 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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