| 摘要 |
In a four-valued read only storage device, each of memory cells arrayed in matrix form at intersections of word lines and bit lines has four metal oxide semiconductor (MOS) transistors. The four MOS transistors have different combinations of two channel impurity profiles and two effective channel lengths in correspondence with storage data. Either data corresponding to the channel impurity profile or data corresponding to the effective channel length is read out from a memory cell by controlling a gate voltage and a drain voltage to be applied to a selected MOS transistor in the memory cell.
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