发明名称 FRAME SYNCHRONIZATION CONTROL CIRCUIT
摘要 PURPOSE: To keep an error between reception and transmission timing within a permissible deviation for a long time even when an oscillation circuit with a low stability is in use by following the phase of a reception frame timing signal with the phase of a recovery frame timing. CONSTITUTION: An oscillated frequency of an oscillation circuit 1 is frequency- divided by a variable frequency divider circuit 2, the result is used for a reception timing signal and it is fed to a frame timing recovery circuit 3. When the circuit 1 has low stability, a deviation is produced between a recovery and a reception frame timing with the elapse of time. An error detection circuit 4 detests a phase error between a recovery frame timing signal being an output of the circuit 3 and a reception frame timing signal being an output of the circuit 2 receiving the reception signal for each prescribed time based on a recovered frame timing signal, an averaging circuit 5 processes the phase error into an error timewise mean value, which is given to a frequency division ratio control circuit 6. Then the circuit 6 applies feedback control to a frequency division ratio of the circuit 2 to allow the reception frame timing to follow the recovery frame timing.
申请公布号 JPH08340312(A) 申请公布日期 1996.12.24
申请号 JP19950170485 申请日期 1995.06.14
申请人 JAPAN RADIO CO LTD 发明人 KOSUGE KOJI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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