| 摘要 |
PURPOSE: To relieve the rule of metallic wiring and increase the operating speed of a semiconductor storage device without increasing the chip size of the device by forming a first wiring layer from a sub-row decoder above gate wiring and bringing the first wiring layer into contact with the gate wiring at the point where a sub-array is divided into two parts in the direction of word lines. CONSTITUTION: On gate wiring, main word lines MWL are arranged to the point at which a sub-array is further divided into two parts from sub-row decoders S.R/D in the same metallic wiring layer and the lines MWL are brought into contact with the gate wiring at the dividing point in the same way as the snap system. Metallic lines M00 and M01 are not arranged in parallel to each other in the direction of the word lines by terminating one metallic line M00 for the output of the sub-row decoder from one end of the sub-array and another metallic line M01 for the output of another sub-row decoder from the other end of the sub-array at the dividing point. When the metallic wires are arranged in such a state, the number of the metallic wires can be reduced to three, one main work line MWL and two lines for snap, in contrast to the four gate lines. |
