| 摘要 |
<p>An output buffer unit for use with a dynamic random access memory includes a first stage (40,41) for generating complementary logic signals. In an intermediate stage (42,43), separate from the generation of the complementary signals, the complementary signals are buffered for application to the output driver stages (44,45,46,47). By separation of the signal generation stages from the buffering stages, the speed of the logic level-to-logic level transitions can be increased.</p> |
