发明名称 PERIOD GENERATION CIRCUIT IN SEMICONDUCTOR TEST EQUIPMENT
摘要 PURPOSE: To realize high speed generation of period using a device of the same level as a conventional one by adding a plurality of waveform data while converting into times with reference to a plurality of waveform output timing pulses and then logically summing the pulses thus obtained to produce a test pattern signal. CONSTITUTION: When a plurality, e.g. four, test pattern period data are outputted in parallel, the output section of a temporary memory means 38 outputs four timing designation data RDT in parallel. A timing generator 31 adds the RDT and outputs the sum to a rate 42. A waveform output timing data is added to the output from an adder 41 to produce a waveform output timing pulse. A waveform generator 33 converts the timing data into times and adds the times thus converted. The pulse and the clock for generating pulse are then logically summed to produce a test pattern signal. Since four pulses can be generated during one cycle even if the parallel period data is generated at the same frequency as conventional one, four times as much generation circuits can be realized as compared with a conventional circuit.
申请公布号 JPH08313601(A) 申请公布日期 1996.11.29
申请号 JP19950142514 申请日期 1995.05.17
申请人 ADVANTEST CORP 发明人 KOBAYASHI MINORU
分类号 G01R31/28;G01R31/3183;G01R31/319;H03B28/00;(IPC1-7):G01R31/318 主分类号 G01R31/28
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