发明名称 COMPETITIVE OPERATION TESTING SYSTEM FOR COMPUTER SYSTEM
摘要 PURPOSE: To perform a high-accuracy test by simultaneously executing the competitive operation test with plural processors in a computer system composed of multiplex processors. CONSTITUTION: Initial setting required for a test instruction is performed with respective instruction processors 20, 21...2n and when the test instruction is issued, an execution control and monitor part 50 stops the instruction processors and reports the stop of instruction processors through a control interface to an inter-processor control part 6. When all the instruction processors are turned to the stop state, the processor control part 6 outputs a start request to execution control and monitor parts 50, 51...5n of all the processors 20, 21...2n. Thus, all the instruction processors 20, 21...2n simultaneously restart operation and execute instructions to be tested. Thus, since the plural processors efficiently execute the competitive operation test at the same timing without fail, high test accuracy can be secured.
申请公布号 JPH08297644(A) 申请公布日期 1996.11.12
申请号 JP19950099206 申请日期 1995.04.25
申请人 HITACHI LTD;HITACHI COMPUTER ELECTRON CO LTD 发明人 ONO MASARU;HONMA KAZUYUKI;SOMEYA SATORU
分类号 G06F15/16;G06F11/22;G06F15/177 主分类号 G06F15/16
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