发明名称 |
Parallel architecture for generating pseudo-random sequences |
摘要 |
A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.
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申请公布号 |
US5574673(A) |
申请公布日期 |
1996.11.12 |
申请号 |
US19940346159 |
申请日期 |
1994.11.29 |
申请人 |
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM |
发明人 |
LOWY, MENAHEM |
分类号 |
F02B75/02;G06F7/58;H03K3/84;(IPC1-7):G06F1/02 |
主分类号 |
F02B75/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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