发明名称 DEMODULATING CIRCUIT OF FSK SIGNAL
摘要 PROBLEM TO BE SOLVED: To constitute a demodulation circuit in a single integrated circuit by reducing the number of the components of the circuit by using a digital circuit which converts received signals into count values. SOLUTION: An amplifier/limiter block 18 processes input analog signals A and outputs the processed signals to a digital counter 20. The counter 20 counts the output of the block 18 by using a clock 22 which is higher in frequency than the transmitting frequency of a transponder 14 and outputs the count values. When noise exists, the counter 20 improves signals by processing the output of the block 18 by means of a DSP filter 24, averages an expected number of periodic counts in a preamble by inputting the improved signals to an averaging device 26, and stores the average count as an adaptive reference count for transfer. An amplitude comparator 30 compares the reference count with a filter 24 and inputs the compared results to a deciding block 32 and the block 32 outputs two bits by converting the two blocks into series signals of a level of logic '0' or '1'. The above-mentioned processing is executed on one integrated circuit 33 upon receiving the input signals so that digital-level output signals may be supplied.
申请公布号 JPH08288969(A) 申请公布日期 1996.11.01
申请号 JP19960011172 申请日期 1996.01.25
申请人 FORD MOTOR CO 发明人 JIYON EFU KENEDEI;SUKOTSUTO OO KIYANBERU;ROORENSU PII KAAKU;DEBITSUDO PII ROODE;RIYUUKU EI PAAKINZU
分类号 B60R25/04;H04L27/10;H04L27/156 主分类号 B60R25/04
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