TIMING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce an area of a circuit by having no complicated circuit and eliminating need of an addition by a method wherein a reset two zero input terminal and a reset two one input terminal are provided in a D type latch, and by using a linear feedback shift register, a circuit for detecting both of a short time delay and a long time delay is provided. SOLUTION: In a linear feedback shift register(LFSR) circuit, each of D type latches D0 to D4 has two reset input terminals R0 , R1 . An output of each latch is set to be 0 when a positive pulse is input to a R0 input terminal and it is set to be 1 when the positive pulse is input to a R1 input terminal. A reset input signal R is connected to the R1 input terminal of the D type latches D1 to D4 and further to the R0 input terminal of the D type latch D0 . When a positive pulse is input to a reset R, an output of the latches D0 to D4 is set to be 11110, and when a clock signal CK is input, the LFSR is circulated a sequence under a cycle condition of reset. With this structure, a simple timing circuit for deciding a plurality of periods is obtained.