发明名称 |
Circuit and method of JTAG testing multichip modules |
摘要 |
A multichip module (10) having one or more IC die (12-18) supports JTAG testing with a plurality of registers (20-26) within each IC die. JTAG testing requires a one cycle delay bypass mode where registers within an IC not under test are bypassed. To support bypass mode when JTAG testing the multichip module on a printed circuit board, a bypass circuit around the multichip module provides the one cycle delay. The bypass circuit monitors the test data signals to the multichip module and enters bypass mode upon detecting a predetermined sequence of logic states during the instruction sequence. Otherwise, the test data signal passes through a plurality of registers within each IC die. The detection may be performed by counting logic states or otherwise monitoring in the instruction sequence.
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申请公布号 |
US5568492(A) |
申请公布日期 |
1996.10.22 |
申请号 |
US19940254846 |
申请日期 |
1994.06.06 |
申请人 |
MOTOROLA, INC. |
发明人 |
FLINT, ANDREW;TRENT, JAMES R.;GRULA, JEROME A. |
分类号 |
G01R31/3185;(IPC1-7):H04B17/00 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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