发明名称 TEST CIRCUIT AND TEST METHOD FOR MICROCOMPUTER
摘要 PURPOSE: To provide a test circuit/method for a microcomputer which uses a single terminal that is used as only an output terminal in a normal operation mode as a test mode setting input terminal and also uses the output buffer of the terminal used as the input terminal in a selection test that is carried out by an LSI tester. CONSTITUTION: This test circuit/method includes a noise elimination part 2 which eliminates the noises when the output signal of an output buffer 1 is compulsively fixed at a power supply potential or a ground potential, a delay element 3 which delays the input signal of the buffer 1 by a time equal to the delay time of the part 2, an inverter 4, a discordance detection part 5 which compares the output of the element 3 with that of the part 2 and outputs a discordance signal if the coincidence is not secured between both outputs, a counter circuit part 6 which counts an discordance signals, and a storage circuit 7 which stores the overflow signal that is produced based on the counting result of the part 6. Then an output terminal 9 is fixed at a power supply or ground potential via an LSI tester, and a test mode is set.
申请公布号 JPH08272639(A) 申请公布日期 1996.10.18
申请号 JP19950072928 申请日期 1995.03.30
申请人 NEC CORP 发明人 SHIIBA TADAAKI
分类号 G06F11/22;G06F11/00;G06F15/78 主分类号 G06F11/22
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