发明名称 BUFFER CONTROL SYSTEM
摘要 PURPOSE: To reduce processings in a portable terminal and a base station, to miniaturize the terminal and an equipment and to lower power consumption by ending a write processing within the first half period of a time division multiple access - time division communication system (TDMA-TDD) frame and ending a read processing within the second half period of the frame. CONSTITUTION: In the processing for which an LAPDC processing part 6a writes transmission control signals to the compression buffer 21 of a TDMA synchronization control part 5a, the write of the LAPDC processing part 6a is processed in the section of 2.5msec of the first half of a transmission frame signal 14 generated by the TDMA synchronization control part 5a and the read of the TDMA synchronization control part 5a is processed in the section of 2.5msec of the second half of the same frame. Similarly, the read of reception control signals from the expansion buffer 22 of the control part 5a by the processing part 6a is processed in the section of 2.5msec of the second half of the same signal 14, the write processing of the control part 5a is performed in the section of 2.5msec of the first half of the same signal 14 and thus, the respective buffers 21 and 22 are realized by one-surface constitution.
申请公布号 JPH08265284(A) 申请公布日期 1996.10.11
申请号 JP19950061376 申请日期 1995.03.20
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KAWAZOE KATSUHIKO;KOBAYASHI SEI;KUBOTA SHUJI;KATO SHUZO
分类号 H03M7/30;H03M13/00;H04J3/00;H04W28/14;H04W88/02;H04W88/08 主分类号 H03M7/30
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