| 摘要 |
A circuit device (DKW) including a processor (DSP), connected via a data bus (DAT) and an address bus (ADR) to the circuit device (DHW), for carrying out the second part of the Viterbi- algorithm, the first part being carried out by the circuit (DHW) device, the latter including storage devices (IN; OUT) for storing the input data (OLM1, OLM2, INC) specified for the processor or for storing output data (NEEM1, NEM2, D1, D2, PRST) accessed by the processor. The circuit (DHW) device also includes a logic circuit (LGT) which forms the output data NEM1, NEM2, D1, D2, PRST) by logic gating fo the input data which is how the circuit (DHW) device processes the first part of the Viterbi algorithm. |
