发明名称 SIGNAL DECODING PROCESSOR
摘要 <p>PURPOSE: To decode a video signal corresponding to plural encoding systems by separating a data sequence received by an interface circuit, transferring the information of a decoding method to a memory and transferring encoded data to a decoding processing circuit. CONSTITUTION: This device is composed of a main processor 3, ROM 1 memory 2, video output control circuit 4, output device 5, voice output control circuit 6, voice output device 7, decoding processing circuit 9 and voice decoding processing circuit 10. The image decoding processing circuit 9 is composed of a decoding program storage memory C, image decoding processor B and memory A. The voice decoding processing circuit 10 is composed of a decoding program memory F, voice decoding processor E and memory D. Since encoded data and decoding program are received from a communication line, at a single decoding terminal, the encoded data can be decoded corresponding to the plural encoding systems without previously storing any decoding program required for decoding.</p>
申请公布号 JPH08256063(A) 申请公布日期 1996.10.01
申请号 JP19950058492 申请日期 1995.03.17
申请人 HITACHI LTD 发明人 NAKAMOTO TAKASHI;WATANABE HIROMI;GUNJI HIROSHI;HASE AKIRA
分类号 H04N19/42;H03M7/30;H04N1/41;H04N7/24;H04N19/00;H04N19/423;H04N19/44;H04N19/70;(IPC1-7):H03M7/30 主分类号 H04N19/42
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