发明名称 PLL CIRCUIT
摘要 PURPOSE: To provide a PLL circuit whose consumed power is small on standby. CONSTITUTION: The PLL circuit 250 has a PLL section 200, a signal change detection circuit 17 and a counter 20. The PLL section 200 generates internal clocks in synchronization with external clocks; the signal change detection circuit 17 detects whether external clocks are fed or not; the counter 20 counts internal clocks during the period when no external clocks are fed; and, when it counts a specified number, it stops oscillation of VCO installed in the PLL section 200. By this, since the oscillation of VCO in a specified period of time after the supply of external clock stops, power consumption on standby is reduced.
申请公布号 JPH08249881(A) 申请公布日期 1996.09.27
申请号 JP19950045572 申请日期 1995.03.06
申请人 NEC CORP 发明人 TAKAI YASUHIRO
分类号 G11C11/407;H03L7/08 主分类号 G11C11/407
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