发明名称 CONNECTING METHOD OF SI CHIP TO PACKAGE
摘要 PURPOSE: To cut down the number of plating steps by a method wherein a solder film having lower melting point than that of solder electrode of a chip on a chip connecting side surface electrode of a package so that the melting point of the solder at the connecting part formed by the fusion-junction of both elements is made higher than that of the solder connecting the package to a substrate. CONSTITUTION: A solder film 1 in thickness of 3-10μm and Sn content of 63wt% is formed on a chip connecting side surface electrode 22 formed on a package 21. Next, when a solder electrode 25 about 150μmϕand Sn content of 5wt% formed on a chip bottom surface is mounted on the electrode 22 so as to be fusion-junctioned at about 340 deg.C, the solder 2 in the junction part becomes Sn 6-8wt% making the melting point higher than that of the solder between the package 21 and the substrate, thereby enabling the possibility of causing defective junction when they are junctioned with each other to be avoided. Through these procedures, the chip and the package can be connected by only one plating step of the solder film, besides, enabling the plating step to be eliminated by immersing in a fusion soldering vessel.
申请公布号 JPH08236579(A) 申请公布日期 1996.09.13
申请号 JP19950039570 申请日期 1995.02.28
申请人 SUMITOMO METAL IND LTD 发明人 MORIYA YOICHI;YAMADE YOSHIAKI
分类号 H01L21/60;H05K3/34;(IPC1-7):H01L21/60 主分类号 H01L21/60
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