<p>An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions. <IMAGE></p>
申请公布号
EP0730224(A2)
申请公布日期
1996.09.04
申请号
EP19960103208
申请日期
1996.03.01
申请人
HAL COMPUTER SYSTEMS, INC.
发明人
SHEBANOW, MICHAEL C.;GMUENDER, JOHN;SIMONE, MICHAEL A.;SZETO, JOHN R.F.S;MARUYAMA, TAKUMI;TOVEY, DEFOREST W.