| 摘要 |
<p>An apparatus receives a reference clock (805) signal that is then applied to a first one of a number of series-connected controllable delay stages (903-1...903-5). The output of each delay stage is a further delayed version of its input, the amount of delay being controlled by a control signal (911). A phase relation between a first preselected one of the plurality of delayed reference clock signals and a second preselected one of the plurality of delayed reference clock signals is measured. Alternatively, it may be a phase relation between the reference clock signal and a preselected one of the plurality of delayed reference clock signals that is measured. The measured phase relation is compared with a desired phase relation, and the difference is an error signal (911) that is fed back to the delay stages for use as the delay control signal. In this manner, the delayed reference clock outputs from the delay stages lock into a very stable desired phase relation with respect to one another. The delayed reference clocks are then transformed by logic circuitry (907) into nonoverlapping phase clocks for use by a switched capacitor sigma-delta modulator. By using the clocks generated in this manner, the switched-capacitor sigma-delta modulated may be operated at rates of 13 MHz or higher.</p> |
