| 摘要 |
PURPOSE: To prevent the deterioration in processing capability of a processor by packing only a data part of a short packet to a reception buffer, processing the short packets into a long packet and transferring the long packets to a data buffer of the processor when the buffer is fully occupied. CONSTITUTION: Upon the receipt of a short packet comprising a flag F, the number of information bytes B, and data I or the like by lien adaptor sections 4-1 to 4-n of a line processing unit 2, the data I are written to a ROM/RAM section 7 of a reception buffer based on a count address by a write address counter 9 of a line adaptor interface section 8 of a line control section 3. An adder circuit 11 counts the count of a byte counter 10 in response to the address and the byte number B and succeeding reception is prepared. Short packet data are sequentially packed in the reception buffer, in which they are processed into long packets and when the long packets are fully occupied in the buffer, the long packets are not transferred to a common buffer of the processor 1 on every reception but subjected to simultaneous DMA transfer thereto to prevent deterioration in the processing capability of the processor 1. |
