| 摘要 |
PURPOSE: To generate an optimum internal clock in accordance with the frequency of an external clock. CONSTITUTION: An output from a delay circuit is delayed by a delay time of the delay circuit in regard to an external clock CLK. In the case where the frequency of the external clock CLK is small, the delay circuit has already risen to an 'H' level at the time of a fall of the external clock CLK since the time of a pulse width of the external clock CLK is longer than the delay time, and an enable signal becomes to be at 'H' level and 'L' level at that time. Therefore a timing circuit 21 for a low speed operation becomes 'enable' and generates an internal clock CLK1. In the case where the frequency of the external clock CLK is large, the enable signal becomes to be at 'L' level and 'H' level and a timing circuit 22 for a high speed operation generates an internal clock CLK2. |
