发明名称 FLATTENING OF INSULATED WIRING LAYER
摘要 PROBLEM TO BE SOLVED: To enhance the planarity of a device inexpensively in a short time. SOLUTION: In a semiconductor device employing a reticulated conductor and a selectively plagiarized interlayer insulating deposition (ILD) in order to enhance the planarity of interconnect layer and a fabrication method therefor, the reticulated conductor 52 is used in place of a solid conductor if the width of solid conductor is wider than a critical width depending on the process and design.
申请公布号 JPH08195395(A) 申请公布日期 1996.07.30
申请号 JP19950255398 申请日期 1995.10.02
申请人 TEXAS INSTR INC <TI> 发明人 MANOJI KUMAA JIEIN;MAIKURU FURANSHISU KISHIYORUMU
分类号 H01L21/3205;H01L21/304;H01L21/3105;H01L21/768;H01L23/528;H01L29/34;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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